Consider the following logic circuit. The output is Y=0 when : [cite: 64, 89]

Q: Consider the following logic circuit. The output is Y=0 when : [cite: 64, 89]

Let the intermediate outputs of the first layers be Y1 and Y2 [cite: 747]: * Top gate is an AND gate with inputs A and B, so Y1 = A cdot B [cite: 747]. * Bottom gate is an OR gate where one input is B and the other is A via a NOT gate, so Y2 = A + B [cite: 747]. * The final layer is a NAND gate with inputs Y1 and Y2, so Y = Y1 cdot Y2[cite: 748]. Let's compute the output Y for all binary input pairs (A, B) [cite: 757]: * For A=0, B=0 Y1 = 0, Y2 = 1 Y = 0 cdot 1 = 1 [cite: 757]. * For A=1, B=0 Y1

Year	2026	2025	2024	Total
Questions	9	15	8	32

Year

2026

2025

2024

Total

Questions

Solution & Explanation

Core Logic

Let the intermediate outputs of the first layers be $Y₁$ $Y_1$ and $Y₂$ $Y_2$ [cite: 747]:

Top gate is an AND gate with inputs $A$ $A$ and $B$ $B$, so $Y₁ = A \cdot B$ $Y_1 = A \cdot B$ [cite: 747].
Bottom gate is an OR gate where one input is $B$ $B$ and the other is $A$ $\bar{A}$ via a NOT gate, so $Y₂ = A + B$ $Y_2 = \bar{A} + B$ [cite: 747].
The final layer is a NAND gate with inputs $Y₁$ $Y_1$ and $Y₂$ $Y_2$, so $Y = Y₁ \cdot Y₂$ $Y = \overline{Y_1 \cdot Y_2}$[cite: 748].

Step 1: Constructing the Truth Table

Let's compute the output $Y$ $Y$ for all binary input pairs $(A, B)$ $(A, B)$ [cite: 757]:

For $A=0, B=0 Y₁ = 0, Y₂ = 1 Y = 0 \cdot 1 = 1$ [cite: 757].
For $A=1, B=0 Y₁ = 0, Y₂ = 0 Y = 0 \cdot 0 = 1$ [cite: 757].
For $A=0, B=1 Y₁ = 0, Y₂ = 1 Y = 0 \cdot 1 = 1$ [cite: 757].
For $A=1, B=1 Y₁ = 1, Y₂ = 1 Y = 1 \cdot 1 = 0$ [cite: 757].

Thus, $Y=0$ $Y=0$ uniquely when $A=1$ $A=1$ and $B=1$ $B=1$[cite: 89, 90, 757].

Pattern Recognition

A NAND gate produces an output of $0$ $0$ if and only if all its inputs are $1$ $1$. Working backward, this instantly sets $Y₁=1$ $Y_1=1$ and $Y₂=1$ $Y_2=1$. For $Y₁ = A \cdot B = 1$ $Y_1 = A \cdot B = 1$, we must have $A=1$ $A=1$ and $B=1$ $B=1$ simultaneously.

Chapter Mix

Class 12 Physics: Semiconductors

Logic Gates solution diagram for Q11 - JEE Main 2025 Evening — The diagram illustrates a combination of an AND gate, an inverter, an OR gate, and a terminal NAND gate with inputs A and B.

More Semiconductors Previous-Year Questions — Page 7

Q49 jee_main_2024_31_jan_evening Logic Gates

The output of the given circuit diagram is

Logic Gates diagram for Q49 - JEE Main 2024 Evening — The image shows a logic circuit composed of NOT gates, OR gates, and a final NOR gate.

A.
A B Y
0 0 0
1 0 0
0 1 0
1 1 1
B.
A B Y
0 0 0
1 0 1
0 1 1
1 1 0
C.
A B Y
0 0 0
1 0 0
0 1 0
1 1 0
D.
A B Y
0 0 0
1 0 0
0 1 1
1 1 0

A	B	Y
0	0	0
1	0	0
0	1	0
1	1	1

A	B	Y
0	0	0
1	0	1
0	1	1
1	1	0

A	B	Y
0	0	0
1	0	0
0	1	0
1	1	0

A	B	Y
0	0	0
1	0	0
0	1	1
1	1	0

Solution

Related Formula

Boolean Algebra expressions for logic gates: NOT: $A$ $\overline{A}$ OR: $A + B$ $A + B$ NOR: $A + B$ $\overline{A + B}$

Core Logic

Analyze the paths from inputs A and B to the final output Y.

Step 1: Intermediate Signals

Top OR gate inputs: $A$ $A$ directly, and $B$ $B$ inverted ( $B$ $\overline{B}$). Top OR gate output: $A + B$ $A + \overline{B}$

Bottom OR gate inputs: $A$ $A$ inverted ( $A$ $\overline{A}$), and $B$ $B$ directly. Bottom OR gate output: $A + B$ $\overline{A} + B$

Step 2: Final Gate Evaluation

The final gate is a NOR gate taking the two intermediate outputs as its inputs.

Y = (A + B) + ( A + B)

Notice that the inner sum simplifies cleanly:

(A + A) + (B + B)

Since $A + A = 1$ $A + \overline{A} = 1$ and $B + B = 1$ $B + \overline{B} = 1$, the inner term is $1 + 1 = 1$ $1 + 1 = 1$.

Y = 1 = 0

Step 3: Conclusion

The output Y is always 0 regardless of the inputs A and B. Checking the truth tables, only option 3 satisfies $Y=0$ $Y=0$ for all conditions.

Pattern Recognition

When a Boolean expression groups a variable and its exact complement together in an OR configuration ( $A$ $A$ and $A$ $\overline{A}$), the result instantly hits logic 1. Feeding 1 into any NOR gate guarantees a 0 output universally.

Chapter Mix

Class 12 Physics: Semiconductor Electronics

Q jee_main_2024_31_jan_morning Logic Gates

Identify the logic operation performed by the given circuit.

Logic Gates diagram for Q32 - JEE Main 2024 Morning — Two inputs passing through NOT gates before entering a NAND gate.

A. $NAND$ $\text{NAND}$
B. $NOR$ $\text{NOR}$
C. $OR$ $\text{OR}$
D. $AND$ $\text{AND}$

Solution

Related Formula

Y = A \cdot B (NAND)

Y = A + B (De Morgan's)

Core Logic

The inputs $A$ $A$ and $B$ $B$ are first passed through individual NOT gates (made from tied-input NAND gates or standard NOT gates). The outputs become $A$ $\overline{A}$ and $B$ $\overline{B}$.

These are then fed into a NAND gate. The final output $Y$ $Y$ is:

Y = A \cdot B

Applying De-Morgan's Law:

Y = A + B

$Y = A + B$ $Y = A + B$

This represents an OR operation.

Pattern Recognition

Bubbled inputs on a NAND gate convert it directly into an OR gate via De-Morgan's laws. (Bubbled NAND = OR).

Chapter Mix

Class 12 Physics: Semiconductor Electronics

Consider the following logic circuit.
The diagram illustrates a combination of an AND gate, an inverter, an OR gate, and a terminal NAND gate with inputs A and B.
The output is $Y=0$ $Y=0$ when : [cite: 64, 89]

Solution & Explanation

Core Logic

Step 1: Constructing the Truth Table

Pattern Recognition

Chapter Mix

Reference Study Guides

More Semiconductors Previous-Year Questions — Page 7

Solution

Related Formula

Core Logic

Step 1: Intermediate Signals

Step 2: Final Gate Evaluation

Step 3: Conclusion

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Pattern Recognition

Chapter Mix

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Consider the following logic circuit. The diagram illustrates a combination of an AND gate, an inverter, an OR gate, and a terminal NAND gate with inputs A and B. The output is Y=0$Y=0$ when : [cite: 64, 89]

Solution & Explanation

Core Logic

Step 1: Constructing the Truth Table

Pattern Recognition

Chapter Mix

Reference Study Guides

More Semiconductors Previous-Year Questions — Page 7

Solution

Related Formula

Core Logic

Step 1: Intermediate Signals

Step 2: Final Gate Evaluation

Step 3: Conclusion

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Pattern Recognition

Chapter Mix

More Semiconductors Questions — jee_main_2025_07_april_evening

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Consider the following logic circuit.
The diagram illustrates a combination of an AND gate, an inverter, an OR gate, and a terminal NAND gate with inputs A and B.
The output is $Y=0$ $Y=0$ when : [cite: 64, 89]