Semiconductors Previous Year Questions — JEE Main Physics
32 past-year Semiconductors questions from JEE Main (Physics).
Q13 (2025)
In the digital circuit shown in the figure, for the given inputs the P and Q values are :
{{IMG1}}
- $\mathrm{P} = 1, \mathrm{Q} = 1$
- $\mathrm{P} = 0, \mathrm{Q} = 0$
- $\mathrm{P} = 0, \mathrm{Q} = 1$
- $\mathrm{P} = 1, \mathrm{Q} = 0$
### Related Formula
Truth relations of basic logic operations:
- NAND operation: $Y = \overline{A \cdot B}$
- NOR operation: $Y = \overline{A + B}$
- NOT operation: $Y = \overline{A}$
- OR operation: $Y = A + B$
### Core Logic
The inputs are:
- Top input = $1$
- Bottom input = $1$
Let's analyze step-by-step from left to right:
1. **First Gate (NAND gate at the top-left):**
- Inputs are $1$ and $1$.
- Output = $\overline{1 \cdot 1} = 0$.
2. **Bottom-left path with NOT gates:**
- Top input ($1$) goes to a NOT gate, producing $0$.
- Bottom input ($1$) goes to a NOT gate, producing $0$.
- These two $0$ values feed into the OR gate:
- Output = $0 + 0 = 0$.
### Step 1: Calculate output P
Now trace the path to $P$:
- The inputs to the top-right AND gate are:
- Output of the top-left NAND gate = $0$
- Output of the bottom-left OR gate = $0$
- Therefore, output $P$ is:
$$P = 0 \cdot 0 = 0$$
### Step 2: Calculate output Q
Now trace the path to $Q$:
- The gate at the bottom-right is a NOR gate with two inputs:
- Input 1: Output of the top-left NAND gate ($0$) inverted by a NOT gate = $\overline{0} = 1$.
- Input 2: Output of the bottom-left OR gate ($0$).
- Passing these inputs ($1$ and $0$) through the final NOR gate:
$$Q = \overline{1 + 0} = \overline{1} = 0$$
Thus, both $P = 0$ and $Q = 0$.
### Pattern Recognition
Sees: Combinational trace with inverted nodes.
Trap: Missing bubbles (NOT gates) representing inversion on internal circuit paths.
Shortcut: The first NAND gate output is $0$ (since both inputs are 1). This $0$ directly goes to the upper AND gate, immediately guaranteeing output $P = 0$ (eliminates options 1 and 4). Now, you only need to evaluate $Q$ to choose between options 2 and 3.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics: Materials, Devices and Simple Circuits
Q11 (2025)
A zener diode with $5\mathrm{~V}$ zener voltage is used to regulate an unregulated dc voltage input of $25\mathrm{~V}$. For a $400\mathrm{~\Omega}$ resistor connected in series, the zener current is found to be 4 times load current. The load current $(I_L)$ and load resistance $(R_L)$ are:
- $I_L = 20\mathrm{~mA}; R_L = 250\mathrm{~\Omega}$
- $I_L = 10\mathrm{~A}; R_L = 0.5\mathrm{~\Omega}$
- $I_L = 0.02\mathrm{~mA}; R_L = 250\mathrm{~\Omega}$
- $I_L = 10\mathrm{~mA}; R_L = 500\mathrm{~\Omega}$
### Related Formula
$$I_{\text{total}} = I_Z + I_L$$
$$I_{\text{total}} = \frac{V_{\text{in}} - V_Z}{R_S}$$
$$R_L = \frac{V_Z}{I_L}$$
### Core Logic
Given parameters:
- Input voltage, $V_{\text{in}} = 25\mathrm{~V}$
- Zener breakdown voltage, $V_Z = 5\mathrm{~V}$
- Series resistor, $R_S = 400\mathrm{~\Omega}$
The voltage drop across the series resistor $R_S$ is:
$$V_{R_S} = V_{\text{in}} - V_Z = 25 - 5 = 20\mathrm{~V}$$
The total series current $I$ is:
$$I_{\text{total}} = \frac{V_{R_S}}{R_S} = \frac{20}{400} = 0.05\mathrm{~A} = 50\mathrm{~mA}$$
We are given that the zener current $I_Z$ is 4 times the load current $I_L$:
$I_Z = 4 I_L$
Since $I_{\text{total}} = I_Z + I_L$:
$$50\mathrm{~mA} = 4 I_L + I_L = 5 I_L \implies I_L = 10\mathrm{~mA}$$
The load resistance connected in parallel with the Zener diode is:
$$R_L = \frac{V_Z}{I_L} = \frac{5\mathrm{~V}}{10 \times 10^{-3}\mathrm{~A}} = 500\mathrm{~\Omega}$$
### Step 1: Final Conclusion
The load current is $10\mathrm{~mA}$ and the load resistance is $500\mathrm{~\Omega}$.
### Pattern Recognition
In any zener regulator problem: first determine the series path current using $I_{\text{total}} = \frac{V_{\text{in}} - V_Z}{R_s}$. Split this total current using the given ratio of $I_Z$ and $I_L$. Finally, determine $R_L$ from $V_Z / I_L$.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
Q163 (2025)
The truth table corresponding to the circuit given below is: {{IMG1}}
- $\text{Table 1}$
- $\text{Table 2}$
- $\text{Table 3}$
- $\text{Table 4}$
### Related Formula
Boolean operators for basic logic gates:
- OR gate:
$Y = A + B$
- AND gate:
$Y = A \cdot B$
### Core Logic
Analyze the schematic:
1. Input lines $A$ and $B$ are linked into an OR gate, yielding output:
$Y = A + B$
2. This term $A + B$ and the original input line $A$ form the inputs to a final AND gate.
3. The final output expression $C$ is therefore:
$$C = A \cdot (A + B)$$
{{SOL_IMG1}}
### Step 1: Construct the Truth Table
Compute output values for each input combination:
- For $A=0, B=0$:
$$C = 0 \cdot (0 + 0) = 0$$
- For $A=1, B=0$:
$$C = 1 \cdot (1 + 0) = 1 \cdot 1 = 1$$
- For $A=0, B=1$:
$$C = 0 \cdot (0 + 1) = 0 \cdot 1 = 0$$
- For $A=1, B=1$:
$$C = 1 \cdot (1 + 1) = 1 \cdot 1 = 1$$
This matches Table 2.
### Pattern Recognition
Using Boolean algebra:
$$C = A \cdot (A + B) = A \cdot A + A \cdot B = A + A \cdot B$$
By absorption law:
$$A + A \cdot B = A$$
So the circuit is equivalent to a simple buffer carrying input $A$. The output $C$ must match input $A$ under all conditions. Checking the options, Table 2 is the one where output $C$ tracks input $A$ directly ($0, 1, 0, 1$).
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductors
Q236 (2025)
In the following circuit, the reading of the ammeter will be (Take Zener breakdown voltage = 4 V) {{IMG1}}
- $24\mathrm{mA}$
- $80\mathrm{mA}$
- $10\mathrm{mA}$
- $60\mathrm{mA}$
### Related Formula
Voltage division across load $R_L$ with series resistance $R_s$ without Zener regulation:
$$V_L = V_{\text{in}} \left( \frac{R_L}{R_s + R_L} \right)$$
If $V_L > V_z$, the Zener diode enters breakdown, and potential across the parallel load is clamped at $V_L = V_z$.
### Core Logic
Verify if Zener diode operates in the breakdown region:
- $V_{\text{in}} = 12 \mathrm{~V}$
- $R_s = 100 \Omega$
- $R_L = 400 \Omega$
Calculate the unregulated voltage:
$$V_1 = 12 \times \left( \frac{400}{100 + 400} \right) = 12 \times \frac{4}{5} = 9.6 \mathrm{~V}$$
Since $V_1 > V_z$ ($9.6 \mathrm{~V} > 4 \mathrm{~V}$), breakdown occurs, and the parallel branch voltage is fixed at $V_z = 4 \mathrm{~V}$.
### Step 1: Calculate Branch Current
The voltage across the $400 \Omega$ load resistor (which is in series with the ammeter) is locked at $4 \mathrm{~V}$.
The current $I$ through the ammeter is:
$$I = \frac{V_z}{R_L} = \frac{4 \mathrm{~V}}{400 \Omega} = 10^{-2} \mathrm{~A} = 10 \mathrm{~mA}$$
### Pattern Recognition
Sees: Parallel Zener diode configuration.
Shortcut: Always calculate the open-circuit load voltage first. If it exceeds $V_z$, use $V_z$ as the branch potential. The branch current is simply $V_z / R_L$. Here, $4 / 400 = 10 \mathrm{~mA}$.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics: Materials, Devices and Simple Circuits
Q8 (2025)
The output voltage in the following circuit is (Consider ideal diode case)
{{IMG1}}
- $10\mathrm{~V}$
- $0\mathrm{~V}$
- $+5\mathrm{~V}$
- $-5\mathrm{~V}$
### Related Formula
For ideal diodes:
- **Forward Bias**: Acts as a closed switch (zero resistance, short circuit).
- **Reverse Bias**: Acts as an open switch (infinite resistance, open circuit).
### Core Logic
Analyzing the bias condition of the diodes based on the applied potential in the schematic:
- Diode $D_1$ is oriented such that its cathode faces the positive terminal ($+5\mathrm{~V}$), making it **Reverse Biased** (no current flows through this branch).
- Diode $D_2$ is oriented such that its anode connects to the $+5\mathrm{~V}$ path, making it **Forward Biased**.
Since $D_2$ is forward-biased and ideal, it acts as a short circuit (resistance $R_D = 0$). Current flows through $D_2$ and through the series resistor.
### Step 1: Calculating output node potential
Because the forward-biased ideal diode $D_2$ connects the node directly to the low-resistance ground loop or the reference resistor drop, the entire $5\mathrm{~V}$ potential drops across the resistor:
$$V_{\text{out}} = 0\mathrm{~V}$$
### Pattern Recognition
Sees: Parallel diode configuration with opposite polarities.
Shortcut: Check polarity. $D_1$ is reverse-biased (open), $D_2$ is forward-biased (short). The output terminal is pulled down to the reference ground, leading directly to $0\mathrm{~V}$. ✓
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
