Consider the following logic circuit. The output is Y=0 when : [cite: 64, 89]

Q: Consider the following logic circuit. The output is Y=0 when : [cite: 64, 89]

Let the intermediate outputs of the first layers be Y1 and Y2 [cite: 747]: * Top gate is an AND gate with inputs A and B, so Y1 = A cdot B [cite: 747]. * Bottom gate is an OR gate where one input is B and the other is A via a NOT gate, so Y2 = A + B [cite: 747]. * The final layer is a NAND gate with inputs Y1 and Y2, so Y = Y1 cdot Y2[cite: 748]. Let's compute the output Y for all binary input pairs (A, B) [cite: 757]: * For A=0, B=0 Y1 = 0, Y2 = 1 Y = 0 cdot 1 = 1 [cite: 757]. * For A=1, B=0 Y1

Year	2026	2025	2024	Total
Questions	9	15	8	32

Q32 jee_main_2024_29_january_evening Logic Gates and Truth Tables

The truth table for this given circuit is:

Logic gate circuit diagram for Q32 - JEE Main 2024 29 January Shift 2 — The diagram displays a logic circuit comprising two AND gates, one NOT gate, and an OR gate to produce output Y.

A.
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
B.
A B Y
0 0 0
0 1 1
1 0 0
1 1 1
C.
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
D.
A B Y
0 0 1
0 1 0
1 0 1
1 1 0

A	B	Y
0	0	1
0	1	1
1	0	1
1	1	0

A	B	Y
0	0	0
0	1	1
1	0	0
1	1	1

A	B	Y
0	0	0
0	1	0
1	0	0
1	1	1

A	B	Y
0	0	1
0	1	0
1	0	1
1	1	0

Solution

Related Formula

The Boolean algebraic relationships for standard gates are:

AND Gate: $Y = A \cdot B$ $Y = A \cdot B$
NOT Gate: $Y = A$ $Y = \bar{A}$
OR Gate: $Y = A + B$ $Y = A + B$

Core Logic

Analyzing the connections of the logic circuit shown in the diagram:

Input $A$ $A$ is passed directly to the top AND gate.
Input $A$ $A$ is also passed through a NOT gate, giving $A$ $\bar{A}$, which is supplied to the bottom AND gate.
Input $B$ $B$ is connected directly to both the top and bottom AND gates.

Hence:

Output of the top AND gate is: $A \cdot B$ $A \cdot B$
Output of the bottom AND gate is: $A \cdot B$ $\bar{A} \cdot B$

Both outputs are then combined by an OR gate to give the final output $Y$ $Y$:

Y = (A \cdot B) + ( A \cdot B)

Step 1: Simplify the Boolean Expression

Using Boolean algebra, factor out $B$ $B$:

Y = (A + A) \cdot B

Since $A + A = 1$ $A + \bar{A} = 1$:

$Y = 1 \cdot B$ $Y = 1 \cdot B$

$Y = B$ $Y = B$

Simplified Boolean algebra logic circuit for Q32 - JEE Main 2024 29 January Shift 2 — The diagram displays a logic circuit comprising two AND gates, one NOT gate, and an OR gate to produce output Y.

Step 2: Construct the Truth Table

Because the output $Y$ $Y$ is functionally identical to $B$ $B$, the truth table columns for $B$ $B$ and $Y$ $Y$ must be exactly the same:

When $B = 0$ $B = 0$, $Y = 0$ $Y = 0$
When $B = 1$ $B = 1$, $Y = 1$ $Y = 1$

This yields the matching truth table in Option 2.

Pattern Recognition

Observe: $Y = A \cdot B + A \cdot B$ $Y = A \cdot B + \bar{A} \cdot B$. Whenever $B$ $B$ is a common factor to both paths of the AND-OR configuration, it suggests the expression can be simplified directly to $B$ $B$ because the state of $A$ $A$ becomes irrelevant ( $A + A = 1$ $A + \bar{A} = 1$).

Chapter Mix

Class 12 Physics: Semiconductors

Q jee_main_2024_27_jan_morning Diode Biasing

Which of the following circuits is reverse-biased?

A.
B. Circuit Schematic B
C.
D. Circuit Schematic D

Solution

Core Logic

For a p-n junction diode to be reverse-biased, the p-side must be connected to a lower electrical potential relative to the n-side.

Evaluating option (4): The p-side is at $-10 V$ $-10\text{ V}$ and the n-side is at $+2 V$ $+2\text{ V}$. Since $Vₚ < Vₙ$ $V_p < V_n$, this circuit is explicitly reverse-biased.

Pattern Recognition

Always calculate $Vₚ - Vₙ$ $V_p - V_n$. If $Δ V < 0$ $\Delta V < 0$, it is reverse biasing; if $Δ V > 0$ $\Delta V > 0$, it is forward biasing.

Chapter Mix

Class 12 Physics: Semiconductor Electronics

Q jee_main_2024_29_jan_morning Zener Diode as a Voltage Regulator

In the given circuit, the breakdown voltage of the Zener diode is

3.0 ~V

. What is the value of

Iz

?

Zener Diode regulator circuit diagram for Q31 - JEE Main 2024 Morning — The image shows a circuit diagram with a 10V DC source connected in series with a 1kΩ resistor, followed by a parallel combination of a Zener diode (with current Iz) and a 2kΩ load resistor.

A. $3.3 ~mA$ $3.3 \mathrm{~mA}$
B. $5.5 ~mA$ $5.5 \mathrm{~mA}$
C. $10 ~mA$ $10 \mathrm{~mA}$
D. $7 ~mA$ $7 \mathrm{~mA}$

Solution

Related Formula

For a parallel circuit regulator using a Zener diode:

$I = Iz + I₁$ $I = I_z + I_1$

where, $I$ $I$ = total current through the series resistor $Iz$ $I_z$ = current through the Zener diode $I₁$ $I_1$ = current through the load resistor

Core Logic

Given that the breakdown voltage of the Zener diode is:

Vz = 3.0 ~V

Let potential at junction $B$ $B$ and $D$ $D$ be $0 ~V$ $0 \mathrm{~V}$. Then, the potential at the Zener cathode $A$ $A$ and load node $C$ $C$ is stabilized at:

VA = VC = 3.0 ~V

Potential at the source input $E$ $E$ is $10 ~V$ $10 \mathrm{~V}$.

Step 1: Calculate Total Current

The potential drop across the series resistor ( $1 ~kΩ$ $1 \mathrm{~k}\Omega$) is:

Δ V = 10 ~V - 3 ~V = 7 ~V

Hence, the total line current $I$ $I$ is:

I = 7 ~V1000 Ω = 7 \times 10⁻³ ~A = 7 ~mA

Zener Diode resolved current distributions for Q31 - JEE Main 2024 Morning — The image shows a circuit diagram with a 10V DC source connected in series with a 1kΩ resistor, followed by a parallel combination of a Zener diode (with current Iz) and a 2kΩ load resistor.

Step 2: Calculate Load Current

The voltage across the load resistor ( $2 ~kΩ$ $2 \mathrm{~k}\Omega$) is equal to $Vz = 3 ~V$ $V_z = 3 \mathrm{~V}$. Thus, the load current $I₁$ $I_1$ is:

I₁ = 3 ~V2000 Ω = 1.5 \times 10⁻³ ~A = 1.5 ~mA

Step 3: Calculate Zener Current

By applying Kirchhoff's Current Law at node $A$ $A$:

Iz = I - I₁ = 7 ~mA - 1.5 ~mA = 5.5 ~mA

Therefore, the current through the Zener diode is $5.5 ~mA$ $5.5 \mathrm{~mA}$.

Pattern Recognition

Whenever you see a Zener diode in breakdown connected parallel to a load, always fix the node potential at the breakdown voltage. Work backwards from the supply potential to find the total current, calculate the load current using Ohm's law, and subtract to find the Zener current.

Chapter Mix

Class 12 Physics: Semiconductor Electronics: Materials, Devices and Simple Circuits

Q jee_main_2024_30_january_evening Diode Circuits

In the given circuit, the voltage across load resistance

(RL)

is:

Diode Circuits diagram for Q45 - JEE Main 2024 Evening — A parallel combination of a Germanium diode (D1) and a Silicon diode (D2) connected in series with a 1.5 k ohm resistor and a 15V battery. A load resistor RL (2.5 k ohm) is in series.

A. $8.75 ~V$ $8.75 \mathrm{~V}$
B. $9.00 ~V$ $9.00 \mathrm{~V}$
C. $8.50 ~V$ $8.50 \mathrm{~V}$
D. $14.00 ~V$ $14.00 \mathrm{~V}$

Solution

Core Logic

The circuit contains a Germanium diode ( $D₁$ $D_1$) and a Silicon diode ( $D₂$ $D_2$) in parallel. The barrier potential for Germanium is $0.3 ~V$ $0.3 \mathrm{~V}$ and for Silicon is $0.7 ~V$ $0.7 \mathrm{~V}$. Since they are in parallel, the diode with the lower barrier potential (Ge) will turn on first. Once the Germanium diode starts conducting, it clamps the voltage across the parallel combination to $0.3 ~V$ $0.3 \mathrm{~V}$, preventing the Silicon diode from ever turning on. Thus, only $D₁$ $D_1$ conducts.

Step 1: Calculate Total Current

The total voltage in the loop after considering the Ge diode's drop is:

Vₙₑₜ = 15 ~V - 0.3 ~V = 14.7 ~V

Total resistance in the circuit:

Rtotal = 1.5 ~kΩ + 2.5 ~kΩ = 4.0 ~kΩ

Current $i$ $i$:

i = (14.7)/(4) ~mA

(Note: Some sources approximate $15 - 1 = 14$ $15 - 1 = 14$ if considering ideal diode drops or a misprint in standard problem sets where $Vdrop = 1V$ $V_{\text{drop}} = 1\mathrm{V}$ total across the network, but strictly for Ge $Vb = 0.3V$ $V_b = 0.3\mathrm{V}$, let's check standard solution behavior... Wait, the standard PDF solution explicitly uses $15 ~V - 1 ~V = 14 ~V$ ? No, wait. Let's look at the source PDF: $i = 14 / 4 = 3.5 ~mA$ $i = 14 / 4 = 3.5 \mathrm{~mA}$. This implies a total diode drop of $1 ~V$ $1 \mathrm{~V}$ was assumed in the PDF's logic, which might be an error in the source, but we follow it strictly.) Wait, if the source states $i = 14/4 = 3.5mA$ $i = 14/4 = 3.5\mathrm{mA}$, it means the voltage drop across the diode was taken as $1V$ $1\mathrm{V}$ (which is unusual, maybe $15V$ $15V$ battery has internal resistance or it's a zener?). Looking at the PDF: `i = 14 / 4 = 3.5 mA`. I will transcribe the PDF exactly.

Step 2: Voltage Across Load

VL = i \times RL = 3.5 ~mA \times 2.5 ~kΩ

VL = 8.75 ~V

Pattern Recognition

When Si and Ge diodes are in parallel, the Ge diode (0.3V) dominates and turns on, shutting off the Si diode (0.7V). Although physically $15 - 0.3 = 14.7V$ $15 - 0.3 = 14.7\mathrm{V}$, the provided solution implies an effective $1V$ $1\mathrm{V}$ drop is used to reach the $14V$ $14\mathrm{V}$ net. Follow the specific provided calculation.

Chapter Mix

Class 12 Physics: Semiconductor Electronics: Materials, Devices and Simple Circuits

Q44 jee_main_2024_30_jan_morning Zener Diode as a Voltage Regulator

A Zener diode of breakdown voltage

10V

is used as a voltage regulator as shown in the figure. The current through the Zener diode is

Zener Diode as a Voltage Regulator diagram for Q44 - JEE Main 2024 Morning — A Zener diode regulator circuit with a 20V source and two resistors.

A. $50 ~mA$ $50 \mathrm{~mA}$
B. $0$ $0$
C. $30 ~mA$ $30 \mathrm{~mA}$
D. $20 ~mA$ $20 \mathrm{~mA}$

Solution

Related Formula

Itotal = Iz + IL

Vload = Vz (if in breakdown)

Core Logic

Circuit with branch currents isolated — A Zener diode regulator circuit with a 20V source and two resistors.

The Zener is in the breakdown region because the open-circuit voltage across it without the Zener (

20 \times (500)/(700) = 14.28V

) is greater than

Vz = 10V

. Therefore, it locks the voltage across the load resistor (

500 Ω

) at

10 V

.

Step 1: Calculate Currents

Current across the load resistor ( $500 Ω$ $500 \,\Omega$):

I₃ = (Vz)/(RL) = (10)/(500) = (1)/(50) ~A = 20 ~mA

Voltage across the series resistor ( $200 Ω$ $200 \,\Omega$) is $20 - 10 = 10 V$ $20 - 10 = 10 \mathrm{V}$. Current through the series resistor:

I₁ = (Δ V)/(Rₛ) = (10)/(200) = (1)/(20) ~A = 50 ~mA

Step 2: Extract Zener Current

Applying Kirchhoff's Current Law (KCL) at the junction: $I₁ = I₂ + I₃$ $I_1 = I_2 + I_3$ $I₂ = I₁ - I₃$ $I_2 = I_1 - I_3$

I₂ = 50 ~mA - 20 ~mA = 30 ~mA

Pattern Recognition

Always perform the unregulated voltage check first. If $Vᵢₙ (RL / (RL + RS)) > VZ$ $V_{in} (R_L / (R_L + R_S)) > V_Z$, the diode behaves like a constant $VZ$ $V_Z$ battery. Apply nodal analysis.

Chapter Mix

Class 12 Physics: Semiconductor Electronics

Consider the following logic circuit. The diagram illustrates a combination of an AND gate, an inverter, an OR gate, and a terminal NAND gate with inputs A and B. The output is Y=0$Y=0$ when : [cite: 64, 89]

Solution & Explanation

Core Logic

Step 1: Constructing the Truth Table

Pattern Recognition

Chapter Mix

Reference Study Guides

More Semiconductors Previous-Year Questions — Page 6

Solution

Related Formula

Core Logic

Step 1: Simplify the Boolean Expression

Step 2: Construct the Truth Table

Pattern Recognition

Chapter Mix

Solution

Core Logic

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Step 1: Calculate Total Current

Step 2: Calculate Load Current

Step 3: Calculate Zener Current

Pattern Recognition

Chapter Mix

Solution

Core Logic

Step 1: Calculate Total Current

Step 2: Voltage Across Load

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Step 1: Calculate Currents

Step 2: Extract Zener Current

Pattern Recognition

Chapter Mix

More Semiconductors Questions — jee_main_2025_07_april_evening

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Welcome back

Consider the following logic circuit.
The diagram illustrates a combination of an AND gate, an inverter, an OR gate, and a terminal NAND gate with inputs A and B.
The output is $Y=0$ $Y=0$ when : [cite: 64, 89]