The truth table for this given circuit is: — jee_main_2024_29_january

Year	2026	2025	2024	Total
Questions	9	15	8	32

Year

2026

2025

2024

Total

Questions

A	B	Y
0	0	1
0	1	1
1	0	1
1	1	0

A	B	Y
0	0	0
0	1	1
1	0	0
1	1	1

A	B	Y
0	0	0
0	1	0
1	0	0
1	1	1

A	B	Y
0	0	1
0	1	0
1	0	1
1	1	0

Solution & Explanation

Related Formula

The Boolean algebraic relationships for standard gates are:

AND Gate: $Y = A \cdot B$ $Y = A \cdot B$
NOT Gate: $Y = A$ $Y = \bar{A}$
OR Gate: $Y = A + B$ $Y = A + B$

Core Logic

Analyzing the connections of the logic circuit shown in the diagram:

Input $A$ $A$ is passed directly to the top AND gate.
Input $A$ $A$ is also passed through a NOT gate, giving $A$ $\bar{A}$, which is supplied to the bottom AND gate.
Input $B$ $B$ is connected directly to both the top and bottom AND gates.

Hence:

Output of the top AND gate is: $A \cdot B$ $A \cdot B$
Output of the bottom AND gate is: $A \cdot B$ $\bar{A} \cdot B$

Both outputs are then combined by an OR gate to give the final output $Y$ $Y$:

Y = (A \cdot B) + ( A \cdot B)

Step 1: Simplify the Boolean Expression

Using Boolean algebra, factor out $B$ $B$:

Y = (A + A) \cdot B

Since $A + A = 1$ $A + \bar{A} = 1$:

$Y = 1 \cdot B$ $Y = 1 \cdot B$

$Y = B$ $Y = B$

Simplified Boolean algebra logic circuit for Q32 - JEE Main 2024 29 January Shift 2 — The diagram displays a logic circuit comprising two AND gates, one NOT gate, and an OR gate to produce output Y.

Step 2: Construct the Truth Table

Because the output $Y$ $Y$ is functionally identical to $B$ $B$, the truth table columns for $B$ $B$ and $Y$ $Y$ must be exactly the same:

When $B = 0$ $B = 0$, $Y = 0$ $Y = 0$
When $B = 1$ $B = 1$, $Y = 1$ $Y = 1$

This yields the matching truth table in Option 2.

Pattern Recognition

Observe: $Y = A \cdot B + A \cdot B$ $Y = A \cdot B + \bar{A} \cdot B$. Whenever $B$ $B$ is a common factor to both paths of the AND-OR configuration, it suggests the expression can be simplified directly to $B$ $B$ because the state of $A$ $A$ becomes irrelevant ( $A + A = 1$ $A + \bar{A} = 1$).

Chapter Mix

Class 12 Physics: Semiconductors

More Semiconductors Previous-Year Questions — Page 7

Q49 jee_main_2024_31_jan_evening Logic Gates

The output of the given circuit diagram is

Logic Gates diagram for Q49 - JEE Main 2024 Evening — The image shows a logic circuit composed of NOT gates, OR gates, and a final NOR gate.

A.
A B Y
0 0 0
1 0 0
0 1 0
1 1 1
B.
A B Y
0 0 0
1 0 1
0 1 1
1 1 0
C.
A B Y
0 0 0
1 0 0
0 1 0
1 1 0
D.
A B Y
0 0 0
1 0 0
0 1 1
1 1 0

A	B	Y
0	0	0
1	0	0
0	1	0
1	1	1

A	B	Y
0	0	0
1	0	1
0	1	1
1	1	0

A	B	Y
0	0	0
1	0	0
0	1	0
1	1	0

A	B	Y
0	0	0
1	0	0
0	1	1
1	1	0

Solution

Related Formula

Boolean Algebra expressions for logic gates: NOT: $A$ $\overline{A}$ OR: $A + B$ $A + B$ NOR: $A + B$ $\overline{A + B}$

Core Logic

Analyze the paths from inputs A and B to the final output Y.

Step 1: Intermediate Signals

Top OR gate inputs: $A$ $A$ directly, and $B$ $B$ inverted ( $B$ $\overline{B}$). Top OR gate output: $A + B$ $A + \overline{B}$

Bottom OR gate inputs: $A$ $A$ inverted ( $A$ $\overline{A}$), and $B$ $B$ directly. Bottom OR gate output: $A + B$ $\overline{A} + B$

Step 2: Final Gate Evaluation

The final gate is a NOR gate taking the two intermediate outputs as its inputs.

Y = (A + B) + ( A + B)

Notice that the inner sum simplifies cleanly:

(A + A) + (B + B)

Since $A + A = 1$ $A + \overline{A} = 1$ and $B + B = 1$ $B + \overline{B} = 1$, the inner term is $1 + 1 = 1$ $1 + 1 = 1$.

Y = 1 = 0

Step 3: Conclusion

The output Y is always 0 regardless of the inputs A and B. Checking the truth tables, only option 3 satisfies $Y=0$ $Y=0$ for all conditions.

Pattern Recognition

When a Boolean expression groups a variable and its exact complement together in an OR configuration ( $A$ $A$ and $A$ $\overline{A}$), the result instantly hits logic 1. Feeding 1 into any NOR gate guarantees a 0 output universally.

Chapter Mix

Class 12 Physics: Semiconductor Electronics

Q jee_main_2024_31_jan_morning Logic Gates

Identify the logic operation performed by the given circuit.

Logic Gates diagram for Q32 - JEE Main 2024 Morning — Two inputs passing through NOT gates before entering a NAND gate.

A. $NAND$ $\text{NAND}$
B. $NOR$ $\text{NOR}$
C. $OR$ $\text{OR}$
D. $AND$ $\text{AND}$

Solution

Related Formula

Y = A \cdot B (NAND)

Y = A + B (De Morgan's)

Core Logic

The inputs $A$ $A$ and $B$ $B$ are first passed through individual NOT gates (made from tied-input NAND gates or standard NOT gates). The outputs become $A$ $\overline{A}$ and $B$ $\overline{B}$.

These are then fed into a NAND gate. The final output $Y$ $Y$ is:

Y = A \cdot B

Applying De-Morgan's Law:

Y = A + B

$Y = A + B$ $Y = A + B$

This represents an OR operation.

Pattern Recognition

Bubbled inputs on a NAND gate convert it directly into an OR gate via De-Morgan's laws. (Bubbled NAND = OR).

Chapter Mix

Class 12 Physics: Semiconductor Electronics

The truth table for this given circuit is:
The diagram displays a logic circuit comprising two AND gates, one NOT gate, and an OR gate to produce output Y.

Solution & Explanation

Related Formula

Core Logic

Step 1: Simplify the Boolean Expression

Step 2: Construct the Truth Table

Pattern Recognition

Chapter Mix

Reference Study Guides

More Semiconductors Previous-Year Questions — Page 7

Solution

Related Formula

Core Logic

Step 1: Intermediate Signals

Step 2: Final Gate Evaluation

Step 3: Conclusion

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Pattern Recognition

Chapter Mix

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The truth table for this given circuit is: The diagram displays a logic circuit comprising two AND gates, one NOT gate, and an OR gate to produce output Y.

Solution & Explanation

Related Formula

Core Logic

Step 1: Simplify the Boolean Expression

Step 2: Construct the Truth Table

Pattern Recognition

Chapter Mix

Reference Study Guides

More Semiconductors Previous-Year Questions — Page 7

Solution

Related Formula

Core Logic

Step 1: Intermediate Signals

Step 2: Final Gate Evaluation

Step 3: Conclusion

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Pattern Recognition

Chapter Mix

More Semiconductors Questions — jee_main_2024_29_january_evening

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The truth table for this given circuit is:
The diagram displays a logic circuit comprising two AND gates, one NOT gate, and an OR gate to produce output Y.