Semiconductors Previous Year Questions — JEE Main Physics
32 past-year Semiconductors questions from JEE Main (Physics) — page 2.
Q18 (2025)
The truth table for the circuit given below is :
{{IMG1}}
- $$\begin{array}{|c|c|c|} \hline A & B & Y \\ \hline 0 & 0 & 0 \\ 0 & 1 & 1 \\ 1 & 0 & 1 \\ 1 & 1 & 0 \\ \hline \end{array}$$
- $$\begin{array}{|c|c|c|} \hline A & B & Y \\ \hline 0 & 0 & 0 \\ 1 & 0 & 0 \\ 1 & 1 & 0 \\ 0 & 1 & 1 \\ \hline \end{array}$$
- $$\begin{array}{|c|c|c|} \hline A & B & Y \\ \hline 0 & 0 & 0 \\ 1 & 0 & 1 \\ 0 & 1 & 0 \\ 1 & 1 & 0 \\ \hline \end{array}$$
- $$\begin{array}{|c|c|c|} \hline A & B & Y \\ \hline 0 & 0 & 0 \\ 1 & 1 & 1 \\ 1 & 0 & 1 \\ 0 & 1 & 1 \\ \hline \end{array}$$
### Related Formula
$$Y = A \cdot \bar{B} + \bar{A} \cdot B = A \oplus B$$
### Core Logic
Analyzing the circuit layout:
1. The top AND gate receives inputs $A$ and $\bar{B}$, yielding output term $A\bar{B}$.
2. The bottom AND gate receives inputs $\bar{A}$ and $B$, yielding output term $\bar{A}B$.
3. These terms pass into a terminal OR gate, producing:
$$Y = A\bar{B} + \bar{A}B$$
{{SOL_IMG1}}
{{SOL_IMG2}}
This is the precise expression for an **XOR (Exclusive OR) gate**. The corresponding truth table gives an output of $1$ only when inputs are mismatched ($0,1$ or $1,0$), and $0$ otherwise. This aligns exactly with Option 1.
### Pattern Recognition
Recognize the symmetric cross-inversion network of gates: $(A \cdot \bar{B}) + (\bar{A} \cdot B)$. This combination structurally builds an XOR logic function.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
Q688 (2025)
Which of the following circuits has the same output as that of the given circuit?
{{IMG1}}
### Core Logic
Let's perform Boolean analysis on the configuration steps mapped below:
$$\mathrm{P} = \mathrm{A} \cdot \bar{\mathrm{B}}$$
$$\mathrm{Q} = \mathrm{A} \cdot \mathrm{B}$$
$$\mathrm{Y} = \overline{\mathrm{P} + \mathrm{Q}} = \overline{\mathrm{A} \cdot \bar{\mathrm{B}} + \mathrm{A} \cdot \mathrm{B}}$$
Factoring using distributive Boolean rules:
$$\mathrm{Y} = \overline{\mathrm{A} \cdot (\mathrm{B} + \bar{\mathrm{B}})} = \overline{\mathrm{A} \cdot 1}$$
$$\mathrm{Y} = \bar{\mathrm{A}}$$
### Step 1: Final Reduction
The expression reduces to a simple inverter (NOT gate) processing input A. This aligns with Circuit (1), matching option (1).
### Pattern Recognition
Identify standard combinations: $(\mathrm{A} \text{ AND NOT } \mathrm{B}) \text{ OR } (\mathrm{A} \text{ AND } \mathrm{B})$ collapses back into simply input A because operand B covers all possible states.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics: Materials, Devices and Simple Circuits
Q753 (2025)
Choose the correct logic circuit for the given truth table having inputs A and B.
<div style="overflow-x: auto; margin: 1rem 0;"><table style="width: 100%; border-collapse: collapse; text-align: left; font-size: 14px;"><thead><tr><th style="border: 1px solid #888; padding: 8px;" colspan="2">Inputs</th><th style="border: 1px solid #888; padding: 8px;">Output</th></tr><tr><th style="border: 1px solid #888; padding: 8px;">$A$</th><th style="border: 1px solid #888; padding: 8px;">$B$</th><th style="border: 1px solid #888; padding: 8px;">$Y$</th></tr></thead><tbody><tr><td style="border: 1px solid #888; padding: 8px;">0</td><td style="border: 1px solid #888; padding: 8px;">0</td><td style="border: 1px solid #888; padding: 8px;">0</td></tr><tr><td style="border: 1px solid #888; padding: 8px;">0</td><td style="border: 1px solid #888; padding: 8px;">1</td><td style="border: 1px solid #888; padding: 8px;">0</td></tr><tr><td style="border: 1px solid #888; padding: 8px;">1</td><td style="border: 1px solid #888; padding: 8px;">0</td><td style="border: 1px solid #888; padding: 8px;">1</td></tr><tr><td style="border: 1px solid #888; padding: 8px;">1</td><td style="border: 1px solid #888; padding: 8px;">1</td><td style="border: 1px solid #888; padding: 8px;">1</td></tr></tbody></table></div>
### Related Formula
Let us inspect the Boolean expression for the output $Y$ from the truth table.
From the table:
- If $A=0$, $Y=0$ regardless of $B$.
- If $A=1$, $Y=1$ regardless of $B$.
Thus, the truth table is represented by the simple direct logical equation:
$Y = A$
### Core Logic
Let's check the Boolean output of the options shown in the question paper:
- **Circuit (1)**: Inputs $A$ and $B$ go into an OR gate, outputting $(A + B)$. This output and $B$ then go to an AND gate.
$$Y = (A + B) \cdot B = A\cdot B + B\cdot B = B(A + 1) = B$$
This gives $Y = B$ (Not matching table).
- **Circuit (2)**: Inputs $A$ and $B$ go into an OR gate, outputting $(A + B)$. This and $A$ then go into an AND gate.
$$Y = (A + B) \cdot A = A\cdot A + A\cdot B = A + A\cdot B = A(1 + B) = A$$
This gives $Y = A$ (Perfect match to the truth table where $Y$ exactly copies $A$).
### Step 1: Verification of Circuit (2)
Let's double-check the truth table values for Circuit (2):
- For $A=0, B=0$: $Y = (0 + 0) \cdot 0 = 0$.
- For $A=0, B=1$: $Y = (0 + 1) \cdot 0 = 0$.
- For $A=1, B=0$: $Y = (1 + 0) \cdot 1 = 1$.
- For $A=1, B=1$: $Y = (1 + 1) \cdot 1 = 1$.
This perfectly matches the given truth table. Therefore, Circuit (2) is correct.
### Pattern Recognition
Identify the logic expression directly from the truth table first! Notice that $Y$ is completely independent of $B$ and strictly equals $A$. This immediately points to any Boolean simplification that collapses to $A$ (such as absorption law: $A(A+B) = A$).
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics: Materials, Devices and Simple Circuits
Q16 (2025)
Consider a n-type semiconductor in which $n_{e}$ and $n_{h}$ are number of electrons and holes, respectively.
(A) Holes are minority carriers
(B) The dopant is a pentavalent atom
(C) $n_{e}n_{h}\ne n_{i}^{2}$ (where $n_{i}$ is number of electrons or holes in semiconductor when it is in intrinsic form)
(D) $n_{e}n_{h}\ge n_{i}^{2}$
(E) The holes are not generated due to the donors
Choose the correct answer from the options given below:
- (A), (C), (D) only
- (A), (C), (E) only
- (A), (B), (E) only
- (A), (B), (C) only
### Related Formula
Mass Action Law:
$$n_e \cdot n_h = n_i^2$$
### Core Logic
Let's analyze each statement for an n-type semiconductor:
- (A) Holes are minority carriers: True, electrons are the majority carriers.
- (B) The dopant is a pentavalent atom: True (like Phosphorus, Arsenic) which provides extra free electrons.
- (C) and (D) contradict the fundamental mass action law $n_e n_h = n_i^2$, so they are False.
- (E) Holes are generated purely due to thermal excitation, not due to donor atoms: True.
### Step 1: Assemble Correct Set
Statements (A), (B), and (E) are explicitly correct.
### Pattern Recognition
Mass action law ($n_e n_h = n_i^2$) holds uniformly for both doped types at thermal equilibrium. In n-type systems, donors directly inject electrons only; holes emerge solely from thermal breakages of lattice bonds.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
Q915 (2025)
The Boolean expression $Y=Aoverline{B}C+overline{A}overline{C}$ can be realised with which of the following gate configurations.
A. One 3-input AND gate, 3 NOT gates and one 2-input OR gate, One 2-input AND gate
B. One 3-input AND gate, 1 NOT gate, One 2-input NOR gate and one 2-input OR gate
C. 3-input OR gate, 3 NOT gates and one 2-input AND gate
Choose the correct answer from the options given below
- B, C Only
- A, B Only
- A, B, C Only
- A, C Only
### Related Formula
Given logical expression:
$$Y = A\overline{B}C + \overline{A}\overline{C}$$
By De Morgan's laws:
$$\overline{A}\cdot\overline{C} = \overline{A+C} \quad \text{(NOR configuration)}$$
### Core Logic
Let's analyze configurations A and B:
* **Configuration A:** Generates $A\overline{B}C$ using one 3-input AND gate and one NOT gate for input $B$. Generates $\overline{A}\overline{C}$ using one 2-input AND gate and two separate NOT gates for inputs $A$ and $C$. Combines both terms using a 2-input OR gate.
*(Total: one 3-input AND, one 2-input AND, three NOT gates, one 2-input OR gate)*.
{{SOL_IMG1}}
### Step 1: Verify Configuration B
* **Configuration B:** Generates $A\overline{B}C$ using one 3-input AND gate and one NOT gate for input $B$. Simplifies the second term $\overline{A}\overline{C}$ into $\overline{A+C}$, realized directly with a single 2-input NOR gate. Combines both sub-circuits using a 2-input OR gate.
*(Total: one 3-input AND, one 2-input NOR, one NOT gate, one 2-input OR gate)*.
{{SOL_IMG2}}
### Step 2: Verify Configuration C
* **Configuration C:** Specifies a 3-input OR gate and a 2-input AND gate at the output, which implements a product-of-sums form rather than the required sum-of-products expression. Hence, Configuration C is invalid.
Both configurations A and B correctly realize the logic function.
### Pattern Recognition
Apply De Morgan's theorem ($\overline{A}\cdot\overline{B} = \overline{A+B}$) to convert negated AND products into standard NOR gate structures, reducing the total gate count.
### Evaluation Rubric / Model Answer
Option B: A, B Only
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
