Semiconductors Previous Year Questions — JEE Main Physics
32 past-year Semiconductors questions from JEE Main (Physics) — page 3.
Q11 (2025)
Consider the following logic circuit.
{{IMG1}}
The output is $Y=0$ when : [cite: 64, 89]
- A=1 and B=1 [cite: 90]
- A=0 and B=1 [cite: 99]
- A=1 and B=0 [cite: 91]
- A=0 and B=0 [cite: 100]
### Core Logic
Let the intermediate outputs of the first layers be $Y_1$ and $Y_2$ [cite: 747]:
* Top gate is an AND gate with inputs $A$ and $B$, so $Y_1 = A \cdot B$ [cite: 747].
* Bottom gate is an OR gate where one input is $B$ and the other is $\bar{A}$ via a NOT gate, so $Y_2 = \bar{A} + B$ [cite: 747].
* The final layer is a NAND gate with inputs $Y_1$ and $Y_2$, so $Y = \overline{Y_1 \cdot Y_2}$[cite: 748].
### Step 1: Constructing the Truth Table
Let's compute the output $Y$ for all binary input pairs $(A, B)$ [cite: 757]:
* For $A=0, B=0 \implies Y_1 = 0, Y_2 = 1 \implies Y = \overline{0 \cdot 1} = 1$ [cite: 757].
* For $A=1, B=0 \implies Y_1 = 0, Y_2 = 0 \implies Y = \overline{0 \cdot 0} = 1$ [cite: 757].
* For $A=0, B=1 \implies Y_1 = 0, Y_2 = 1 \implies Y = \overline{0 \cdot 1} = 1$ [cite: 757].
* For $A=1, B=1 \implies Y_1 = 1, Y_2 = 1 \implies Y = \overline{1 \cdot 1} = 0$ [cite: 757].
Thus, $Y=0$ uniquely when $A=1$ and $B=1$[cite: 89, 90, 757].
### Pattern Recognition
A NAND gate produces an output of $0$ if and only if all its inputs are $1$. Working backward, this instantly sets $Y_1=1$ and $Y_2=1$. For $Y_1 = A \cdot B = 1$, we must have $A=1$ and $B=1$ simultaneously.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductors
Q15 (2025)
The output of the circuit is low (zero) for : {{IMG1}}
(A) X = 0, Y = 0
(B) X = 0, Y = 1
(C) X = 1, Y = 0
(D) X = 1, Y = 1
Choose the correct answer from the options given below:
- (A), (C) and (D) only
- (A), (B) and (C) only
- (B), (C) and (D) only
- (A), (B) and (D) only
### Core Logic
Let us check the gate outputs row-by-row to find the boolean expression or map the truth table values: {{SOL_IMG1}}
$$\begin{array}{ccc} X & Y & \text{Output} \\ \hline 0 & 0 & 1 \\ 0 & 1 & 0 \\ 1 & 0 & 0 \\ 1 & 1 & 0 \end{array}$$
The output is low (zero) for configurations (B) $X=0, Y=1$, (C) $X=1, Y=0$, and (D) $X=1, Y=1$. Therefore, options (B), (C) and (D) only are correct.
### Pattern Recognition
The truth table profile matches a standard NOR logic configuration where the output is 1 only when all input lines are completely low.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
Q6 (2025)
Consider the following statements:
A. The junction area of solar cell is made very narrow compared to a photo diode.
B. Solar cells are not connected with any external bias.
C. LED is made of lightly doped p-n junction.
D. Increase of forward current results in continuous increase of LED light intensity.
E. LEDs have to be connected in forward bias for emission of light.
Choose the correct answer from the options given below :
- B, D, E Only
- A, C Only
- A, C, E Only
- B, E Only
### Core Logic
Let's analyze each statement conceptually:
Statement A: Solar cells require a wide surface layer area to intercept maximum sunlight illumination, so junction area is large.
* Statement B: True. Solar cells operate spontaneously to provide power to loads without requiring external bias voltage.
* Statement C: False. LEDs are made of heavily doped junctions to maximize recombination probability.
* Statement D: False. Beyond a critical limit, high currents cause heating that drops efficiency, so emission intensity does not increase infinitely.
* Statement E: True. Forward biasing allows minority injection leading to radiative recombination.
### Step 1: Selecting Option
Since statements B and E are purely accurate, the correct grouping option is B, E Only.
### Pattern Recognition
Remember: LEDs = Forward Bias, Photodiodes = Reverse Bias, Solar Cells = Zero External Bias.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics: Materials, Devices and Simple Circuits
Q1215 (2025)
In the circuit shown here, assuming threshold voltage of diode is negligibly small, then voltage $\mathrm{V_{AB}}$ is correctly represented by:
{{IMG1}}
- $\mathrm{V_{AB}}\text{ would be zero at all times}$
### Core Logic
Analyze the cycle profile behavior of the input voltage waveform $V = V_0 \sin \omega t$:
1. **Positive Half Cycle**: Node A achieves a positive potential relative to node B. Under this configuration, the diode enters a **Reverse Biased (R.B.)** state, acting as an open switch circuit block. Since no current conducts across the resistive path, the potential difference tracked directly mirrors the input wave voltage.
2. **Negative Half Cycle**: Node A goes negative relative to node B. This transitions the diode into a **Forward Biased (F.B.)** condition, acting as a closed short-circuit bypass path. Consequently, the potential settles down immediately to zero.
This behavior is visualized through the input/output tracking waveforms below:
{{SOL_IMG1}}
{{SOL_IMG2}}
### Step 1: Selection
Matching this half-wave rectified configuration precisely selects option (4).
### Pattern Recognition
When solving diode waveform problems, replace the diode mentally with an open circuit during reverse bias and a short circuit during forward bias to quickly observe the resulting output profile.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
Q1290 (2025)
{{IMG1}}
For the circuit shown above, equivalent GATE is :
- OR gate
- NOT gate
- AND gate
- NAND gate
### Core Logic
Evaluating the given logic gate diagram combination step-by-step for all input permutations yields the following truth table :
<div style="overflow-x: auto; margin: 1rem 0;"><table style="width: 100%; border-collapse: collapse; text-align: left; font-size: 14px;"><thead><tr><th style="border: 1px solid #888; padding: 8px;">Input A</th><th style="border: 1px solid #888; padding: 8px;">Input B</th><th style="border: 1px solid #888; padding: 8px;">Output Y</th></tr></thead><tbody><tr><td style="border: 1px solid #888; padding: 8px;">0</td><td style="border: 1px solid #888; padding: 8px;">0</td><td style="border: 1px solid #888; padding: 8px;">0</td></tr><tr><td style="border: 1px solid #888; padding: 8px;">0</td><td style="border: 1px solid #888; padding: 8px;">1</td><td style="border: 1px solid #888; padding: 8px;">1</td></tr><tr><td style="border: 1px solid #888; padding: 8px;">1</td><td style="border: 1px solid #888; padding: 8px;">0</td><td style="border: 1px solid #888; padding: 8px;">1</td></tr><tr><td style="border: 1px solid #888; padding: 8px;">1</td><td style="border: 1px solid #888; padding: 8px;">1</td><td style="border: 1px solid #888; padding: 8px;">1</td></tr></tbody></table></div>
This behavior matches an OR Gate configuration perfectly.
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
