Consider the following logic circuit. The output is Y=0 when : [cite: 64, 89]

Q: Consider the following logic circuit. The output is Y=0 when : [cite: 64, 89]

Let the intermediate outputs of the first layers be Y1 and Y2 [cite: 747]: * Top gate is an AND gate with inputs A and B, so Y1 = A cdot B [cite: 747]. * Bottom gate is an OR gate where one input is B and the other is A via a NOT gate, so Y2 = A + B [cite: 747]. * The final layer is a NAND gate with inputs Y1 and Y2, so Y = Y1 cdot Y2[cite: 748]. Let's compute the output Y for all binary input pairs (A, B) [cite: 757]: * For A=0, B=0 Y1 = 0, Y2 = 1 Y = 0 cdot 1 = 1 [cite: 757]. * For A=1, B=0 Y1

Year	2026	2025	2024	Total
Questions	9	15	8	32

Q11 jee_main_2025_02_april_morning Zener Diode and Voltage Regulation

A zener diode with

5~V

zener voltage is used to regulate an unregulated dc voltage input of

25~V

. For a

400~Ω

resistor connected in series, the zener current is found to be 4 times load current. The load current

(IL)

and load resistance

(RL)

are:

A. $IL = 20~mA; RL = 250~Ω$
B. $IL = 10~A; RL = 0.5~Ω$
C. $IL = 0.02~mA; RL = 250~Ω$
D. $IL = 10~mA; RL = 500~Ω$

Solution

Related Formula

Itotal = IZ + IL

Itotal = Vᵢₙ - VZRS

RL = (VZ)/(IL)

Core Logic

Given parameters:

Input voltage, $Vᵢₙ = 25~V$ $V_{\text{in}} = 25\mathrm{~V}$
Zener breakdown voltage, $VZ = 5~V$ $V_Z = 5\mathrm{~V}$
Series resistor, $RS = 400~Ω$ $R_S = 400\mathrm{~\Omega}$

The voltage drop across the series resistor $RS$ $R_S$ is:

VRS = Vᵢₙ - VZ = 25 - 5 = 20~V

The total series current $I$ $I$ is:

Itotal = VRSRS = (20)/(400) = 0.05~A = 50~mA

We are given that the zener current $IZ$ $I_Z$ is 4 times the load current $IL$ $I_L$:

$IZ = 4 IL$ $I_Z = 4 I_L$

Since $Itotal = IZ + IL$ $I_{\text{total}} = I_Z + I_L$:

50~mA = 4 IL + IL = 5 IL IL = 10~mA

The load resistance connected in parallel with the Zener diode is:

RL = (VZ)/(IL) = 5~V10 \times 10⁻³~A = 500~Ω

Step 1: Final Conclusion

The load current is $10~mA$ $10\mathrm{~mA}$ and the load resistance is $500~Ω$ $500\mathrm{~\Omega}$.

Pattern Recognition

In any zener regulator problem: first determine the series path current using $Itotal = Vᵢₙ - VZRₛ$ . Split this total current using the given ratio of $IZ$ $I_Z$ and $IL$ $I_L$. Finally, determine $RL$ $R_L$ from $VZ / IL$ $V_Z / I_L$.

Chapter Mix

Class 12 Physics: Semiconductor Electronics

Q jee_main_2025_03_april_evening Logic Gates and Truth Tables

The truth table corresponding to the circuit given below is:

Logic gate circuit diagram for Q13 - JEE Main 2025 Evening — Diagram showing a combination of logic gates connected to inputs A and B resulting in output C.

A. $Table 1$ $\text{Table 1}$
B. $Table 2$ $\text{Table 2}$
C. $Table 3$ $\text{Table 3}$
D. $Table 4$ $\text{Table 4}$

Solution

Related Formula

Boolean operators for basic logic gates:

OR gate:

$Y = A + B$ $Y = A + B$

AND gate:

$Y = A \cdot B$ $Y = A \cdot B$

Core Logic

Analyze the schematic:

Input lines $A$ $A$ and $B$ $B$ are linked into an OR gate, yielding output:

$Y = A + B$ $Y = A + B$

This term $A + B$ $A + B$ and the original input line $A$ $A$ form the inputs to a final AND gate.
The final output expression $C$ $C$ is therefore:

C = A \cdot (A + B)

Logic Gates and Truth Tables — Diagram showing a combination of logic gates connected to inputs A and B resulting in output C.

Step 1: Construct the Truth Table

Compute output values for each input combination:

For $A=0, B=0$ $A=0, B=0$:

C = 0 \cdot (0 + 0) = 0

For $A=1, B=0$ $A=1, B=0$:

C = 1 \cdot (1 + 0) = 1 \cdot 1 = 1

For $A=0, B=1$ $A=0, B=1$:

C = 0 \cdot (0 + 1) = 0 \cdot 1 = 0

For $A=1, B=1$ $A=1, B=1$:

C = 1 \cdot (1 + 1) = 1 \cdot 1 = 1

This matches Table 2.

Pattern Recognition

Using Boolean algebra:

C = A \cdot (A + B) = A \cdot A + A \cdot B = A + A \cdot B

By absorption law:

A + A \cdot B = A

So the circuit is equivalent to a simple buffer carrying input $A$ $A$. The output $C$ $C$ must match input $A$ $A$ under all conditions. Checking the options, Table 2 is the one where output $C$ $C$ tracks input $A$ $A$ directly ( $0, 1, 0, 1$ $0, 1, 0, 1$).

Chapter Mix

Class 12 Physics: Semiconductors

Q jee_main_2025_07_april_morning Zener Diode

In the following circuit, the reading of the ammeter will be (Take Zener breakdown voltage = 4 V)

Zener regulator circuit for Q11 - JEE Main 2025 Morning — A schematic showing a 12V supply connected to a series 100 ohm resistor, which then branches into a parallel Zener diode and a 400 ohm resistor in series with an ammeter.

A. $24mA$ $24\mathrm{mA}$
B. $80mA$ $80\mathrm{mA}$
C. $10mA$ $10\mathrm{mA}$
D. $60mA$ $60\mathrm{mA}$

Solution

Related Formula

Voltage division across load $RL$ $R_L$ with series resistance $Rₛ$ $R_s$ without Zener regulation:

VL = Vᵢₙ ( (RL)/(Rₛ + RL) )

If $VL > Vz$ $V_L > V_z$, the Zener diode enters breakdown, and potential across the parallel load is clamped at $VL = Vz$ $V_L = V_z$.

Core Logic

Verify if Zener diode operates in the breakdown region:

$Vᵢₙ = 12 ~V$ $V_{\text{in}} = 12 \mathrm{~V}$
$Rₛ = 100 Ω$ $R_s = 100 \Omega$
$RL = 400 Ω$ $R_L = 400 \Omega$

Calculate the unregulated voltage:

V₁ = 12 \times ( (400)/(100 + 400) ) = 12 \times (4)/(5) = 9.6 ~V

Since $V₁ > Vz$ $V_1 > V_z$ ( $9.6 ~V > 4 ~V$ $9.6 \mathrm{~V} > 4 \mathrm{~V}$), breakdown occurs, and the parallel branch voltage is fixed at $Vz = 4 ~V$ $V_z = 4 \mathrm{~V}$.

Step 1: Calculate Branch Current

The voltage across the $400 Ω$ $400 \Omega$ load resistor (which is in series with the ammeter) is locked at $4 ~V$ $4 \mathrm{~V}$.

The current $I$ $I$ through the ammeter is:

I = (Vz)/(RL) = 4 ~V400 Ω = 10⁻² ~A = 10 ~mA

Pattern Recognition

Sees: Parallel Zener diode configuration. Shortcut: Always calculate the open-circuit load voltage first. If it exceeds $Vz$ $V_z$, use $Vz$ $V_z$ as the branch potential. The branch current is simply $Vz / RL$ $V_z / R_L$. Here, $4 / 400 = 10 ~mA$ $4 / 400 = 10 \mathrm{~mA}$.

Chapter Mix

Class 12 Physics: Semiconductor Electronics: Materials, Devices and Simple Circuits

Q8 jee_main_2025_08_april_evening Diodes

The output voltage in the following circuit is (Consider ideal diode case)

Diodes circuit diagram for Q8 - JEE Main 2025 Evening — A schematic of a circuit showing an input voltage, two diodes D1 and D2 connected in parallel paths, a resistor, and the output node V_out.

A. $10~V$ $10\mathrm{~V}$
B. $0~V$ $0\mathrm{~V}$
C. $+5~V$ $+5\mathrm{~V}$
D. $-5~V$ $-5\mathrm{~V}$

Solution

Related Formula

For ideal diodes:

Forward Bias: Acts as a closed switch (zero resistance, short circuit).
Reverse Bias: Acts as an open switch (infinite resistance, open circuit).

Core Logic

Analyzing the bias condition of the diodes based on the applied potential in the schematic:

Diode $D₁$ $D_1$ is oriented such that its cathode faces the positive terminal ( $+5~V$ $+5\mathrm{~V}$), making it Reverse Biased (no current flows through this branch).
Diode $D₂$ $D_2$ is oriented such that its anode connects to the $+5~V$ $+5\mathrm{~V}$ path, making it Forward Biased.

Since $D₂$ $D_2$ is forward-biased and ideal, it acts as a short circuit (resistance $RD = 0$ $R_D = 0$). Current flows through $D₂$ $D_2$ and through the series resistor.

Step 1: Calculating output node potential

Because the forward-biased ideal diode $D₂$ $D_2$ connects the node directly to the low-resistance ground loop or the reference resistor drop, the entire $5~V$ $5\mathrm{~V}$ potential drops across the resistor:

Vout = 0~V

Pattern Recognition

Sees: Parallel diode configuration with opposite polarities. Shortcut: Check polarity. $D₁$ $D_1$ is reverse-biased (open), $D₂$ $D_2$ is forward-biased (short). The output terminal is pulled down to the reference ground, leading directly to $0~V$ $0\mathrm{~V}$. ✓

Chapter Mix

Class 12 Physics: Semiconductor Electronics

Q18 jee_main_2025_29_jan_evening Logic Gates

The truth table for the circuit given below is :

Logic Gates circuit diagram for Q18 - JEE Main 2025 Evening — The image shows a digital logic circuit containing multiple interconnected logic gates with input terminals A and B and output terminal Y.

A. $array|c|c|c| A & B & Y 0 & 0 & 0 0 & 1 & 1 1 & 0 & 1 1 & 1 & 0 array$
B. $array|c|c|c| A & B & Y 0 & 0 & 0 1 & 0 & 0 1 & 1 & 0 0 & 1 & 1 array$
C. $array|c|c|c| A & B & Y 0 & 0 & 0 1 & 0 & 1 0 & 1 & 0 1 & 1 & 0 array$
D. $array|c|c|c| A & B & Y 0 & 0 & 0 1 & 1 & 1 1 & 0 & 1 0 & 1 & 1 array$

Solution

Related Formula

Y = A \cdot B + A \cdot B = A B

Core Logic

Analyzing the circuit layout:

The top AND gate receives inputs $A$ $A$ and $B$ $\bar{B}$, yielding output term $A B$ $A\bar{B}$.
The bottom AND gate receives inputs $A$ $\bar{A}$ and $B$ $B$, yielding output term $AB$ $\bar{A}B$.
These terms pass into a terminal OR gate, producing:

Y = A B + AB

Logic Boolean Analysis diagram for Q18 - JEE Main 2025 Evening — The image shows a digital logic circuit containing multiple interconnected logic gates with input terminals A and B and output terminal Y.

This is the precise expression for an XOR (Exclusive OR) gate. The corresponding truth table gives an output of $1$ $1$ only when inputs are mismatched ( $0,1$ $0,1$ or $1,0$ $1,0$), and $0$ $0$ otherwise. This aligns exactly with Option 1.

Pattern Recognition

Recognize the symmetric cross-inversion network of gates: $(A \cdot B) + ( A \cdot B)$ $(A \cdot \bar{B}) + (\bar{A} \cdot B)$. This combination structurally builds an XOR logic function.

Chapter Mix

Class 12 Physics: Semiconductor Electronics

Consider the following logic circuit. The diagram illustrates a combination of an AND gate, an inverter, an OR gate, and a terminal NAND gate with inputs A and B. The output is Y=0$Y=0$ when : [cite: 64, 89]

Solution & Explanation

Core Logic

Step 1: Constructing the Truth Table

Pattern Recognition

Chapter Mix

Reference Study Guides

More Semiconductors Previous-Year Questions — Page 3

Solution

Related Formula

Core Logic

Step 1: Final Conclusion

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Step 1: Construct the Truth Table

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Step 1: Calculate Branch Current

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Step 1: Calculating output node potential

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Pattern Recognition

Chapter Mix

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Welcome back

Consider the following logic circuit.
The diagram illustrates a combination of an AND gate, an inverter, an OR gate, and a terminal NAND gate with inputs A and B.
The output is $Y=0$ $Y=0$ when : [cite: 64, 89]