A zener diode with 5~V zener voltage is used to regulate an unregulated dc voltage input of 25~V. For a 400~Omega…

Year	2026	2025	2024	Total
Questions	9	15	8	32

Year

2026

2025

2024

Total

Questions

Solution & Explanation

Related Formula

Itotal = IZ + IL

Itotal = Vᵢₙ - VZRS

RL = (VZ)/(IL)

Core Logic

Given parameters:

Input voltage, $Vᵢₙ = 25~V$ $V_{\text{in}} = 25\mathrm{~V}$
Zener breakdown voltage, $VZ = 5~V$ $V_Z = 5\mathrm{~V}$
Series resistor, $RS = 400~Ω$ $R_S = 400\mathrm{~\Omega}$

The voltage drop across the series resistor $RS$ $R_S$ is:

VRS = Vᵢₙ - VZ = 25 - 5 = 20~V

The total series current $I$ $I$ is:

Itotal = VRSRS = (20)/(400) = 0.05~A = 50~mA

We are given that the zener current $IZ$ $I_Z$ is 4 times the load current $IL$ $I_L$:

$IZ = 4 IL$ $I_Z = 4 I_L$

Since $Itotal = IZ + IL$ $I_{\text{total}} = I_Z + I_L$:

50~mA = 4 IL + IL = 5 IL IL = 10~mA

The load resistance connected in parallel with the Zener diode is:

RL = (VZ)/(IL) = 5~V10 \times 10⁻³~A = 500~Ω

Step 1: Final Conclusion

The load current is $10~mA$ $10\mathrm{~mA}$ and the load resistance is $500~Ω$ $500\mathrm{~\Omega}$.

Pattern Recognition

In any zener regulator problem: first determine the series path current using $Itotal = Vᵢₙ - VZRₛ$ . Split this total current using the given ratio of $IZ$ $I_Z$ and $IL$ $I_L$. Finally, determine $RL$ $R_L$ from $VZ / IL$ $V_Z / I_L$.

Chapter Mix

Class 12 Physics: Semiconductor Electronics

More Semiconductors Previous-Year Questions — Page 7

Q49 jee_main_2024_31_jan_evening Logic Gates

The output of the given circuit diagram is

Logic Gates diagram for Q49 - JEE Main 2024 Evening — The image shows a logic circuit composed of NOT gates, OR gates, and a final NOR gate.

A.
A B Y
0 0 0
1 0 0
0 1 0
1 1 1
B.
A B Y
0 0 0
1 0 1
0 1 1
1 1 0
C.
A B Y
0 0 0
1 0 0
0 1 0
1 1 0
D.
A B Y
0 0 0
1 0 0
0 1 1
1 1 0

A	B	Y
0	0	0
1	0	0
0	1	0
1	1	1

A	B	Y
0	0	0
1	0	1
0	1	1
1	1	0

A	B	Y
0	0	0
1	0	0
0	1	0
1	1	0

A	B	Y
0	0	0
1	0	0
0	1	1
1	1	0

Solution

Related Formula

Boolean Algebra expressions for logic gates: NOT: $A$ $\overline{A}$ OR: $A + B$ $A + B$ NOR: $A + B$ $\overline{A + B}$

Core Logic

Analyze the paths from inputs A and B to the final output Y.

Step 1: Intermediate Signals

Top OR gate inputs: $A$ $A$ directly, and $B$ $B$ inverted ( $B$ $\overline{B}$). Top OR gate output: $A + B$ $A + \overline{B}$

Bottom OR gate inputs: $A$ $A$ inverted ( $A$ $\overline{A}$), and $B$ $B$ directly. Bottom OR gate output: $A + B$ $\overline{A} + B$

Step 2: Final Gate Evaluation

The final gate is a NOR gate taking the two intermediate outputs as its inputs.

Y = (A + B) + ( A + B)

Notice that the inner sum simplifies cleanly:

(A + A) + (B + B)

Since $A + A = 1$ $A + \overline{A} = 1$ and $B + B = 1$ $B + \overline{B} = 1$, the inner term is $1 + 1 = 1$ $1 + 1 = 1$.

Y = 1 = 0

Step 3: Conclusion

The output Y is always 0 regardless of the inputs A and B. Checking the truth tables, only option 3 satisfies $Y=0$ $Y=0$ for all conditions.

Pattern Recognition

When a Boolean expression groups a variable and its exact complement together in an OR configuration ( $A$ $A$ and $A$ $\overline{A}$), the result instantly hits logic 1. Feeding 1 into any NOR gate guarantees a 0 output universally.

Chapter Mix

Class 12 Physics: Semiconductor Electronics

Q jee_main_2024_31_jan_morning Logic Gates

Identify the logic operation performed by the given circuit.

Logic Gates diagram for Q32 - JEE Main 2024 Morning — Two inputs passing through NOT gates before entering a NAND gate.

A. $NAND$ $\text{NAND}$
B. $NOR$ $\text{NOR}$
C. $OR$ $\text{OR}$
D. $AND$ $\text{AND}$

Solution

Related Formula

Y = A \cdot B (NAND)

Y = A + B (De Morgan's)

Core Logic

The inputs $A$ $A$ and $B$ $B$ are first passed through individual NOT gates (made from tied-input NAND gates or standard NOT gates). The outputs become $A$ $\overline{A}$ and $B$ $\overline{B}$.

These are then fed into a NAND gate. The final output $Y$ $Y$ is:

Y = A \cdot B

Applying De-Morgan's Law:

Y = A + B

$Y = A + B$ $Y = A + B$

This represents an OR operation.

Pattern Recognition

Bubbled inputs on a NAND gate convert it directly into an OR gate via De-Morgan's laws. (Bubbled NAND = OR).

Chapter Mix

Class 12 Physics: Semiconductor Electronics

Solution & Explanation

Related Formula

Core Logic

Step 1: Final Conclusion

Pattern Recognition

Chapter Mix

Reference Study Guides

More Semiconductors Previous-Year Questions — Page 7

Solution

Related Formula

Core Logic

Step 1: Intermediate Signals

Step 2: Final Gate Evaluation

Step 3: Conclusion

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Pattern Recognition

Chapter Mix

More Semiconductors Questions — jee_main_2025_02_april_morning

Select Your Target Exam

Full Mock Test Hub

Topic-wise Practice Hub

Exam Analysis Tools

Chapter Weightage & Trends

Topic-wise Practice Hub

JEE Main Exam Papers

Chapter Weightage Board

Formula Recognition

Exam Questions

Select an Exam

Solution & Explanation

Related Formula

Core Logic

Step 1: Final Conclusion

Pattern Recognition

Chapter Mix

Reference Study Guides

More Semiconductors Previous-Year Questions — Page 7

Solution

Related Formula

Core Logic

Step 1: Intermediate Signals

Step 2: Final Gate Evaluation

Step 3: Conclusion

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Pattern Recognition

Chapter Mix

More Semiconductors Questions — jee_main_2025_02_april_morning

Select Your Target Exam

Full Mock Test Hub

Topic-wise Practice Hub

Exam Analysis Tools

Chapter Weightage & Trends

Topic-wise Practice Hub

JEE Main Exam Papers

Chapter Weightage Board

Formula Recognition

Exam Questions

Select an Exam

Welcome back