Semiconductors Previous Year Questions — JEE Main Physics
32 past-year Semiconductors questions from JEE Main (Physics) — page 5.
Q44 (2024)
A Zener diode of breakdown voltage $10\mathrm{V}$ is used as a voltage regulator as shown in the figure. The current through the Zener diode is
{{IMG1}}
- $50 \mathrm{~mA}$
- $0$
- $30 \mathrm{~mA}$
- $20 \mathrm{~mA}$
### Related Formula
$$I_{\text{total}} = I_z + I_L$$
$$V_{\text{load}} = V_z \quad (\text{if in breakdown})$$
### Core Logic
{{SOL_IMG1}}
The Zener is in the breakdown region because the open-circuit voltage across it without the Zener ($20 \times \frac{500}{700} = 14.28\mathrm{V}$) is greater than $V_z = 10\mathrm{V}$. Therefore, it locks the voltage across the load resistor ($500 \,\Omega$) at $10 \mathrm{V}$.
### Step 1: Calculate Currents
Current across the load resistor ($500 \,\Omega$):
$$I_3 = \frac{V_z}{R_L} = \frac{10}{500} = \frac{1}{50} \mathrm{~A} = 20 \mathrm{~mA}$$
Voltage across the series resistor ($200 \,\Omega$) is $20 - 10 = 10 \mathrm{V}$.
Current through the series resistor:
$$I_1 = \frac{\Delta V}{R_s} = \frac{10}{200} = \frac{1}{20} \mathrm{~A} = 50 \mathrm{~mA}$$
### Step 2: Extract Zener Current
Applying Kirchhoff's Current Law (KCL) at the junction:
$I_1 = I_2 + I_3$
$I_2 = I_1 - I_3$
$$I_2 = 50 \mathrm{~mA} - 20 \mathrm{~mA} = 30 \mathrm{~mA}$$
### Pattern Recognition
Always perform the unregulated voltage check first. If $V_{in} (R_L / (R_L + R_S)) > V_Z$, the diode behaves like a constant $V_Z$ battery. Apply nodal analysis.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
Q49 (2024)
The output of the given circuit diagram is
{{IMG1}}
- <div style="overflow-x: auto; margin: 1rem 0;"><table style="width: 100%; border-collapse: collapse; text-align: center; font-size: 14px;"><thead><tr><th style="border: 1px solid #888; padding: 4px;">A</th><th style="border: 1px solid #888; padding: 4px;">B</th><th style="border: 1px solid #888; padding: 4px;">Y</th></tr></thead><tbody><tr><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">0</td></tr><tr><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">0</td></tr><tr><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">0</td></tr><tr><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">1</td></tr></tbody></table></div>
- <div style="overflow-x: auto; margin: 1rem 0;"><table style="width: 100%; border-collapse: collapse; text-align: center; font-size: 14px;"><thead><tr><th style="border: 1px solid #888; padding: 4px;">A</th><th style="border: 1px solid #888; padding: 4px;">B</th><th style="border: 1px solid #888; padding: 4px;">Y</th></tr></thead><tbody><tr><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">0</td></tr><tr><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">1</td></tr><tr><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">1</td></tr><tr><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">0</td></tr></tbody></table></div>
- <div style="overflow-x: auto; margin: 1rem 0;"><table style="width: 100%; border-collapse: collapse; text-align: center; font-size: 14px;"><thead><tr><th style="border: 1px solid #888; padding: 4px;">A</th><th style="border: 1px solid #888; padding: 4px;">B</th><th style="border: 1px solid #888; padding: 4px;">Y</th></tr></thead><tbody><tr><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">0</td></tr><tr><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">0</td></tr><tr><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">0</td></tr><tr><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">0</td></tr></tbody></table></div>
- <div style="overflow-x: auto; margin: 1rem 0;"><table style="width: 100%; border-collapse: collapse; text-align: center; font-size: 14px;"><thead><tr><th style="border: 1px solid #888; padding: 4px;">A</th><th style="border: 1px solid #888; padding: 4px;">B</th><th style="border: 1px solid #888; padding: 4px;">Y</th></tr></thead><tbody><tr><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">0</td></tr><tr><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">0</td></tr><tr><td style="border: 1px solid #888; padding: 4px;">0</td><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">1</td></tr><tr><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">1</td><td style="border: 1px solid #888; padding: 4px;">0</td></tr></tbody></table></div>
### Related Formula
Boolean Algebra expressions for logic gates:
NOT: $\overline{A}$
OR: $A + B$
NOR: $\overline{A + B}$
### Core Logic
Analyze the paths from inputs A and B to the final output Y.
{{SOL_IMG1}}
### Step 1: Intermediate Signals
Top OR gate inputs: $A$ directly, and $B$ inverted ($\overline{B}$).
Top OR gate output: $A + \overline{B}$
Bottom OR gate inputs: $A$ inverted ($\overline{A}$), and $B$ directly.
Bottom OR gate output: $\overline{A} + B$
### Step 2: Final Gate Evaluation
The final gate is a NOR gate taking the two intermediate outputs as its inputs.
$$Y = \overline{(A + \overline{B}) + (\overline{A} + B)}$$
Notice that the inner sum simplifies cleanly:
$$(A + \overline{A}) + (B + \overline{B})$$
Since $A + \overline{A} = 1$ and $B + \overline{B} = 1$, the inner term is $1 + 1 = 1$.
$$Y = \overline{1} = 0$$
### Step 3: Conclusion
The output Y is always 0 regardless of the inputs A and B. Checking the truth tables, only option 3 satisfies $Y=0$ for all conditions.
### Pattern Recognition
When a Boolean expression groups a variable and its exact complement together in an OR configuration ($A$ and $\overline{A}$), the result instantly hits logic 1. Feeding 1 into any NOR gate guarantees a 0 output universally.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
Q1982 (2024)
Identify the logic operation performed by the given circuit.
{{IMG1}}
- $\text{NAND}$
- $\text{NOR}$
- $\text{OR}$
- $\text{AND}$
### Related Formula
$$Y = \overline{A \cdot B} \quad \text{(NAND)}$$
$$Y = \overline{A} + \overline{B} \quad \text{(De Morgan's)}$$
### Core Logic
The inputs $A$ and $B$ are first passed through individual NOT gates (made from tied-input NAND gates or standard NOT gates). The outputs become $\overline{A}$ and $\overline{B}$.
These are then fed into a NAND gate.
The final output $Y$ is:
$$Y = \overline{\overline{A} \cdot \overline{B}}$$
Applying De-Morgan's Law:
$$Y = \overline{\overline{A}} + \overline{\overline{B}}$$
$Y = A + B$
This represents an OR operation.
### Pattern Recognition
Bubbled inputs on a NAND gate convert it directly into an OR gate via De-Morgan's laws. (Bubbled NAND = OR).
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
Q2087 (2026)
The given circuit works as :
{{IMG1}}
- AND gate
- NOR gate
- NAND gate
- OR gate
### Related Formula
De Morgan's Laws:
$$\overline{A} + \overline{B} = \overline{A \cdot B}$$
$$\overline{\overline{A}} = A$$
### Core Logic
Analyzing the circuit diagram:
{{SOL_IMG1}}
- Top branch has a NOT gate on A, so $P = \overline{A}$
- Bottom branch has a NOT gate on B, so $Q = \overline{B}$
- They enter a NOR gate, giving output $R = \overline{\overline{A} + \overline{B}}$
- Finally, R passes through a NOT gate to give $S = \overline{R}$
### Step 1: Boolean Simplification
$$R = \overline{\overline{A} + \overline{B}} = \overline{\overline{AB}} = AB$$
$$S = \overline{R} = \overline{AB}$$
The expression $\overline{AB}$ is the Boolean expression for a NAND gate.
### Pattern Recognition
Two NOTs feeding into a NOR equals an AND gate ($AB$). Adding a final NOT gate turns the AND into a NAND.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
Q34 (2026)
Find the correct combination of A, B, C and D inputs which can cause the LED to glow.
{{IMG1}}
- 0100
- 0011
- 1000
- 1101
### Related Formula
$$\text{NOR Gate: } \overline{A+B}, \quad \text{NAND Gate: } \overline{A \cdot B}$$
### Core Logic
{{SOL_IMG1}}
LED will glow in forward biasing when point P is at higher potential (1) and point Q is at lower potential (0).
Testing option (4) [1101]:
- Inputs A=1, B=1 through NOR and NAND gates yield P = 1.
- Inputs C=1, D=0 through NOR gate yields Q = 0.
- Forward bias established, LED glows.
### Pattern Recognition
Sees: Logic gates combination with LED forward biasing condition.
Shortcut: Check forward bias requirement (P=1, Q=0) for each option combination.
Check: Option (4) satisfies the condition. ✓
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
