The correct truth table for the given input data of the following logic gate is :

Q: The correct truth table for the given input data of the following logic gate is :

Applying De Morgan's Law: Analyzing the expression step by step: 1. Upper branch: A and B pass through NAND gate arrow A cdot B. 2. Lower branch: C and D pass through OR gate arrow (C + D). 3. Combined in AND gate followed by NOT gate (NAND equivalent output stage): Testing conditions for Option (2): - For A=1, B=1, C=0, D=1 (1 cdot 1) + (0 + 1) = 1 + 0 = 1. - For A=0, B=0, C=1, D=1 (0 cdot 0) + (1 + 1) = 0 + 0 = 0. - For A=1, B=0, C=1, D=0 (1 cdot 0) + (1 + 0) = 0 + 0 = 0. - For A=1, B=1, C=1,

Inputs	Output
1	1	0	1	1
0	0	1	1	0
1	0	1	0	1
1	1	1	1	0

Inputs

Output

Inputs	Output
1	1	0	1	1
0	0	1	1	0
1	0	1	0	0
1	1	1	1	1

Inputs

Output

Inputs	Output
1	1	0	1	0
0	0	1	1	0
1	0	1	0	1
1	1	1	1	1

Inputs

Output

Inputs	Output
1	1	0	1	0
0	0	1	1	1
1	0	1	0	1
1	1	1	1	1

Inputs

Output

Solution & Explanation

Related Formula

Y = ( A \cdot B) \cdot (C + D)

Applying De Morgan's Law:

Y = (A \cdot B) + ( C + D)

Core Logic

Analyzing the expression step by step:

Upper branch: $A$ $A$ and $B$ $B$ pass through NAND gate $arrow A \cdot B$ $\rightarrow \overline{A \cdot B}$.
Lower branch: $C$ $C$ and $D$ $D$ pass through OR gate $arrow (C + D)$ $\rightarrow (C + D)$.
Combined in AND gate followed by NOT gate (NAND equivalent output stage):

Y = ( A \cdot B) \cdot (C + D) = (A \cdot B) + ( C + D)

Testing conditions for Option (2):

For $A=1, B=1, C=0, D=1 (1 \cdot 1) + ( 0 + 1) = 1 + 0 = 1$ .
For $A=0, B=0, C=1, D=1 (0 \cdot 0) + ( 1 + 1) = 0 + 0 = 0$ .
For $A=1, B=0, C=1, D=0 (1 \cdot 0) + ( 1 + 0) = 0 + 0 = 0$ .
For $A=1, B=1, C=1, D=1 (1 \cdot 1) + ( 1 + 1) = 1 + 0 = 1$ .

Logic circuit truth table evaluation diagram for Q35 - JEE Main 2026 Evening — The figure illustrates a combined logic circuit with inputs A, B, C, D feeding into AND, OR, and NOT gates to produce output Y.

Step 1: Final Conclusion

Option (2) presents the correct truth table matching the evaluated output values.

Pattern Recognition

Boolean reduction: $X \cdot Y = X + Y$ where $X = A \cdot B$ $X = A \cdot B$ and $Y = C+D$ $Y = C+D$. Hence $Y = (A \cdot B) + ( C+D)$ $Y = (A \cdot B) + (\overline{C+D})$.

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Class 12 Physics: Semiconductor Electronics

More Semiconductor Electronics Previous-Year Questions — Page 7

Q49 jee_main_2024_31_jan_evening Logic Gates

The output of the given circuit diagram is

Logic Gates diagram for Q49 - JEE Main 2024 Evening — The image shows a logic circuit composed of NOT gates, OR gates, and a final NOR gate.

A.
A B Y
0 0 0
1 0 0
0 1 0
1 1 1
B.
A B Y
0 0 0
1 0 1
0 1 1
1 1 0
C.
A B Y
0 0 0
1 0 0
0 1 0
1 1 0
D.
A B Y
0 0 0
1 0 0
0 1 1
1 1 0

A	B	Y
0	0	0
1	0	0
0	1	0
1	1	1

A	B	Y
0	0	0
1	0	1
0	1	1
1	1	0

A	B	Y
0	0	0
1	0	0
0	1	0
1	1	0

A	B	Y
0	0	0
1	0	0
0	1	1
1	1	0

Solution

Related Formula

Boolean Algebra expressions for logic gates: NOT: $A$ $\overline{A}$ OR: $A + B$ $A + B$ NOR: $A + B$ $\overline{A + B}$

Core Logic

Analyze the paths from inputs A and B to the final output Y.

Step 1: Intermediate Signals

Top OR gate inputs: $A$ $A$ directly, and $B$ $B$ inverted ( $B$ $\overline{B}$). Top OR gate output: $A + B$ $A + \overline{B}$

Bottom OR gate inputs: $A$ $A$ inverted ( $A$ $\overline{A}$), and $B$ $B$ directly. Bottom OR gate output: $A + B$ $\overline{A} + B$

Step 2: Final Gate Evaluation

The final gate is a NOR gate taking the two intermediate outputs as its inputs.

Y = (A + B) + ( A + B)

Notice that the inner sum simplifies cleanly:

(A + A) + (B + B)

Since $A + A = 1$ $A + \overline{A} = 1$ and $B + B = 1$ $B + \overline{B} = 1$, the inner term is $1 + 1 = 1$ $1 + 1 = 1$.

Y = 1 = 0

Step 3: Conclusion

The output Y is always 0 regardless of the inputs A and B. Checking the truth tables, only option 3 satisfies $Y=0$ $Y=0$ for all conditions.

Pattern Recognition

When a Boolean expression groups a variable and its exact complement together in an OR configuration ( $A$ $A$ and $A$ $\overline{A}$), the result instantly hits logic 1. Feeding 1 into any NOR gate guarantees a 0 output universally.

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Class 12 Physics: Semiconductor Electronics

Q jee_main_2024_31_jan_morning Logic Gates

Identify the logic operation performed by the given circuit.

Logic Gates diagram for Q32 - JEE Main 2024 Morning — Two inputs passing through NOT gates before entering a NAND gate.

A. $NAND$ $\text{NAND}$
B. $NOR$ $\text{NOR}$
C. $OR$ $\text{OR}$
D. $AND$ $\text{AND}$

Solution

Related Formula

Y = A \cdot B (NAND)

Y = A + B (De Morgan's)

Core Logic

The inputs $A$ $A$ and $B$ $B$ are first passed through individual NOT gates (made from tied-input NAND gates or standard NOT gates). The outputs become $A$ $\overline{A}$ and $B$ $\overline{B}$.

These are then fed into a NAND gate. The final output $Y$ $Y$ is:

Y = A \cdot B

Applying De-Morgan's Law:

Y = A + B

$Y = A + B$ $Y = A + B$

This represents an OR operation.

Pattern Recognition

Bubbled inputs on a NAND gate convert it directly into an OR gate via De-Morgan's laws. (Bubbled NAND = OR).

Chapter Mix

Class 12 Physics: Semiconductor Electronics

The correct truth table for the given input data of the following logic gate is :
The figure illustrates a combined logic circuit with inputs A, B, C, D feeding into AND, OR, and NOT gates to produce output Y.

Solution & Explanation

Related Formula

Core Logic

Step 1: Final Conclusion

Pattern Recognition

Chapter Mix

Reference Study Guides

More Semiconductor Electronics Previous-Year Questions — Page 7

Solution

Related Formula

Core Logic

Step 1: Intermediate Signals

Step 2: Final Gate Evaluation

Step 3: Conclusion

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Pattern Recognition

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The correct truth table for the given input data of the following logic gate is : The figure illustrates a combined logic circuit with inputs A, B, C, D feeding into AND, OR, and NOT gates to produce output Y.

Solution & Explanation

Related Formula

Core Logic

Step 1: Final Conclusion

Pattern Recognition

Chapter Mix

Reference Study Guides

More Semiconductor Electronics Previous-Year Questions — Page 7

Solution

Related Formula

Core Logic

Step 1: Intermediate Signals

Step 2: Final Gate Evaluation

Step 3: Conclusion

Pattern Recognition

Chapter Mix

Solution

Related Formula

Core Logic

Pattern Recognition

Chapter Mix

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The correct truth table for the given input data of the following logic gate is :
The figure illustrates a combined logic circuit with inputs A, B, C, D feeding into AND, OR, and NOT gates to produce output Y.