Consider a n-type semiconductor in which n_e$n_{e}$ and n_h$n_{h}$ are number of electrons and holes, respectively.
(A) Holes are minority carriers
(B) The dopant is a pentavalent atom
(C) n_en_hne n_i^2$n_{e}n_{h}\ne n_{i}^{2}$ (where n_i$n_{i}$ is number of electrons or holes in semiconductor when it is in intrinsic form)
(D) n_en_hge n_i^2$n_{e}n_{h}\ge n_{i}^{2}$
(E) The holes are not generated due to the donors
Choose the correct answer from the options given below:
A.(A), (C), (D) only
B.(A), (C), (E) only
C.(A), (B), (E) only
D.(A), (B), (C) only
Solution & Explanation
### Related Formula
Mass Action Law:
n_e cdot n_h = n_i^2$n_e \cdot n_h = n_i^2$
### Core Logic
Let's analyze each statement for an n-type semiconductor:
- (A) Holes are minority carriers: True, electrons are the majority carriers.
- (B) The dopant is a pentavalent atom: True (like Phosphorus, Arsenic) which provides extra free electrons.
- (C) and (D) contradict the fundamental mass action law n_e n_h = n_i^2$n_e n_h = n_i^2$, so they are False.
- (E) Holes are generated purely due to thermal excitation, not due to donor atoms: True.
### Step 1: Assemble Correct Set
Statements (A), (B), and (E) are explicitly correct.
### Pattern Recognition
Mass action law (n_e n_h = n_i^2$n_e n_h = n_i^2$) holds uniformly for both doped types at thermal equilibrium. In n-type systems, donors directly inject electrons only; holes emerge solely from thermal breakages of lattice bonds.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
Keywords:#n-type semiconductor in which ne and nh are number#JEE Main 2025 Evening Q16#Semiconductor Electronics JEE Main 2025#Extrinsic Semiconductors JEE Main 2025
More Semiconductor Electronics Previous-Year Questions — Page 2
Q152025Logic Gates
The output of the circuit is low (zero) for : The figure contains a digital combination logic gate configuration with input variables X and Y.
(A) X = 0, Y = 0
(B) X = 0, Y = 1
(C) X = 1, Y = 0
(D) X = 1, Y = 1
Choose the correct answer from the options given below:
A. (A), (C) and (D) only
B. (A), (B) and (C) only
C. (B), (C) and (D) only
D. (A), (B) and (D) only
Solution
### Core Logic
Let us check the gate outputs row-by-row to find the boolean expression or map the truth table values: The figure contains a digital combination logic gate configuration with input variables X and Y.beginarrayccc X & Y & textOutput \hline 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 0 & 0 \ 1 & 1 & 0 endarray$\begin{array}{ccc} X & Y & \text{Output} \\hline 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 0 & 0 \ 1 & 1 & 0 \end{array}$
The output is low (zero) for configurations (B) X=0, Y=1$X=0, Y=1$, (C) X=1, Y=0$X=1, Y=0$, and (D) X=1, Y=1$X=1, Y=1$. Therefore, options (B), (C) and (D) only are correct.
### Pattern Recognition
The truth table profile matches a standard NOR logic configuration where the output is 1 only when all input lines are completely low.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
Q152025Diode Rectifiers
In the circuit shown here, assuming threshold voltage of diode is negligibly small, then voltage mathrmV_AB$\mathrm{V_{AB}}$ is correctly represented by:
An AC source connected across an orientation circuit involving an ideal junction diode.
A.mathrmV_ABtext would be zero at all times$\mathrm{V_{AB}}\text{ would be zero at all \times}$
B. {{IMG_OPT2}}
C. {{IMG_OPT3}}
D. {{IMG_OPT4}}
Solution
### Core Logic
Analyze the cycle profile behavior of the input voltage waveform V = V_0 sin omega t$V = V_0 \sin \omega t$:
1. **Positive Half Cycle**: Node A achieves a positive potential relative to node B. Under this configuration, the diode enters a **Reverse Biased (R.B.)** state, acting as an open switch circuit block. Since no current conducts across the resistive path, the potential difference tracked directly mirrors the input wave voltage.
2. **Negative Half Cycle**: Node A goes negative relative to node B. This transitions the diode into a **Forward Biased (F.B.)** condition, acting as a closed short-circuit bypass path. Consequently, the potential settles down immediately to zero.
This behavior is visualized through the input/output tracking waveforms below:
An AC source connected across an orientation circuit involving an ideal junction diode.An AC source connected across an orientation circuit involving an ideal junction diode.
### Step 1: Selection
Matching this half-wave rectified configuration precisely selects option (4).
### Pattern Recognition
When solving diode waveform problems, replace the diode mentally with an open circuit during reverse bias and a short circuit during forward bias to quickly observe the resulting output profile.
### Evaluation Rubric / Model Answer
null
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
Q152025Logic Gates
The image features a digital circuit blueprint constructed from basic logic gates with inputs A and B mapped to an output Y.
For the circuit shown above, equivalent GATE is : [cite: 1, 2]
A. OR gate
B. NOT gate
C. AND gate
D. NAND gate
Solution
### Core Logic
Evaluating the given logic gate diagram combination step-by-step for all input permutations yields the following truth table :
Input A
Input B
Output Y
0
0
0
0
1
1
1
0
1
1
1
1
This behavior matches an OR Gate configuration perfectly.
### Chapter Mix
Class 12 Physics: Semiconductor Electronics
More Semiconductor Electronics Questions — jee_main_2025_04_april_evening
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